In the prior art, electronic components can sustain very strong constant or cyclic environmental and mechanical stress, such as for example in methods of transportation involving airplanes, trains, or boats. In the mentioned methods of transportation, temperatures can range from −55° C. to 125° C., and the relative humidity of a cabinet in which these electronic components are located can reach about 80%.
It is therefore important, for reasons of operational safety, to verify that the assembly of electronic components assembled on a printed circuit board support such stress. For this, we generally use test beds to detect any incipient cracks in the solder connections that provide the electrical connection and mechanical link between the component and the printed circuit board. These test beds are used during accelerated aging tests involving thermo-mechanical or vibration stress. Dummy components (meaning only the boxes with dummy chips) are used to carry out the thermo-mechanical or vibration accelerated aging tests because only the solder connections are tested here. By “daisy chain”, we mean the combination of a number of solder connections, electrically interconnected, each one to the next, to the same component. The set forms a measurable overall electrical resistance. Using daisy chained dummy components allows the user to focus on the failures occurring at the solder connections. This technique allows a resistor measurement to be associated to a state of damage in the soldered connections.
To qualify a circuit, we measure the failure time of its solder connections and thus the life span of its assembly. Then we deduce a reliability of the assembly resulting from a statistical study. In other words, it is necessary to test many components of the same type in order to have meaningful results. It is therefore important to have a device comprising a large number of measurement methods to be able to monitor a large number of components simultaneously.
Various devices currently exist for performing these tests. One example of such a device is described in the document “RoHS/ELV recycling constraints: a Lead Free electronics qualification procedure for automotive and industrial quality and reliability”. This document presents a test bench for electronic monitoring in parallel with various tested components.
Another device example is described in the document “Application of FPGA units in combined temperature cycle and vibration reliability tests of lead free interconnections”. This document presents an acquisition device that monitors a set of parallel paths.
However, with the devices presented in the prior art, a crack or failure is detected only when there is a total break in the solder connection. Also, it is necessary to duplicate the testing device completely for each electronic circuit board that is tested and to change the device for each test performed. The testing device is installed on the electronic circuit board to be tested, and it undergoes the same thermo-mechanical or vibration stress as the electronic components under test. This duplication causes rather significant overhead due to the risk of non-relevant measurements and premature damage to the circuit performing the measurements.
Moreover, another drawback of the prior art is the late detection of state change events, or peaks (high variation in the resistor value over a very short time), in the electrical resistor with a number of solder connections electrically interconnected, each one to the next, on the same component (daisy chain). Such prior art devices require significant resources in terms of electrical energy in order to power multiple programmable logical circuits at the same time.
The known devices apply the IPC-SM-785 standard or detect only the first electrical resistor peaks, also called an event. However, this standard is sometimes poorly adapted for detecting failures because it takes as criteria temporal sequences of peaks corresponding to a given time and resistor pattern. This pattern or protocol may lead to incorrect conclusions. Typically, an incorrect conclusion is not detecting a break in a tested circuit because the previous pattern is strictly enforced. The result is that a circuit will be assumed as destroyed after N cycles, although it will really have failed well before. To solve this problem, in the invention, rather than it being imperative to follow the criteria (time and/or resistor pattern or protocols) in the standard, the preference criteria are modified in terms of quantities so as to adapt to the different types of tests and mechanisms of damage to the associated soldered connections. Ultimately, with the invention, each programmed criterion is adjusted to the tests to be performed.